12class dma : 
public sc_core::sc_module
 
   15    tlm_utils::simple_initiator_socket<dma, DEFAULT_TLM_BUSWIDTH> socket;
 
   17    tlm::tlm_dmi dmi_data;
 
   20    dma(
const sc_core::sc_module_name& name): sc_core::sc_module(name), socket(
"socket") { dmi_valid = 
false; }
 
   26        tlm::tlm_generic_payload 
trans;
 
   28        if (dmi_valid && 
addr >= dmi_data.get_start_address() && (
addr + size) < dmi_data.get_end_address()) {
 
   29            if (
is_write && dmi_data.is_write_allowed()) {
 
   31                unsigned char* 
ptr = dmi_data.get_dmi_ptr();
 
   34            } 
else if (!
is_write && dmi_data.is_read_allowed()) {
 
   36                unsigned char* 
ptr = dmi_data.get_dmi_ptr();
 
   42        trans.set_command(
is_write ? tlm::TLM_WRITE_COMMAND : tlm::TLM_READ_COMMAND);
 
   44        trans.set_data_ptr(
reinterpret_cast<unsigned char*
>(data));
 
   45        trans.set_data_length(size);
 
   46        trans.set_streaming_width(size);
 
   47        trans.set_byte_enable_length(0);
 
   48        trans.set_dmi_allowed(
false);
 
   49        trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
 
   51        sc_core::sc_time delay(sc_core::SC_ZERO_TIME);
 
   52        socket->b_transport(
trans, delay);
 
   54        if (
trans.is_dmi_allowed()) {
 
   55            dmi_valid = socket->get_direct_mem_ptr(
trans, dmi_data);