quic/qbox
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qemu-components
common
include
libqemu-cxx
target
riscv.h
1
/*
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* This file is part of libqemu-cxx
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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* Author: GreenSocs 2021
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#pragma once
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#include <libqemu-cxx/libqemu-cxx.h>
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namespace
qemu {
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class
CpuRiscv
:
public
Cpu
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{
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public
:
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static
constexpr
const
char
*
const
TYPE =
"riscv-cpu"
;
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using
MipUpdateCallbackFn = std::function<
void
(
uint32_t
)>;
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CpuRiscv
() =
default
;
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CpuRiscv
(
const
CpuRiscv
&) =
default
;
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CpuRiscv
(
const
Object
&
o
):
Cpu
(
o
) {}
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void
set_mip_update_callback(MipUpdateCallbackFn
cb
);
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};
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class
CpuRiscv32
:
public
CpuRiscv
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{
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public
:
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CpuRiscv32
() =
default
;
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CpuRiscv32
(
const
CpuRiscv32
&) =
default
;
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CpuRiscv32
(
const
Object
&
o
):
CpuRiscv
(
o
) {}
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};
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class
CpuRiscv64
:
public
CpuRiscv
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{
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public
:
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CpuRiscv64
() =
default
;
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CpuRiscv64
(
const
CpuRiscv64
&) =
default
;
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CpuRiscv64
(
const
Object
&
o
):
CpuRiscv
(
o
) {}
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};
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class
CpuRiscv64SiFiveX280
:
public
CpuRiscv
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{
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public
:
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CpuRiscv64SiFiveX280
() =
default
;
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CpuRiscv64SiFiveX280
(
const
CpuRiscv64SiFiveX280
&) =
default
;
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CpuRiscv64SiFiveX280
(
const
Object
&
o
):
CpuRiscv
(
o
) {}
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};
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}
// namespace qemu
QemuTargetSocket
Definition
target.h:160
qemu::CpuRiscv32
Definition
riscv.h:29
qemu::CpuRiscv64SiFiveX280
Definition
riscv.h:45
qemu::CpuRiscv64
Definition
riscv.h:37
qemu::CpuRiscv
Definition
riscv.h:15
qemu::Cpu
Definition
libqemu-cxx.h:664
qemu::Object
Definition
libqemu-cxx.h:229
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